– 2.5V +/-0.2V Power Supply for DDR400/333
– 2.4V~2.7V Power Supply for DDR500
– Up to 250 MHz Clock Frequency
– Double Data Rate architecture; two data transfers per clock cycle
– Differential clock inputs (CLK and CLK )
– DQS is edge-aligned with data for Read; center-aligned with data for Write
– CAS Latency: 2, 2.5, 3 and 4
– Burst Length: 2, 4 and 8
– Auto Refresh and Self Refresh
– Precharged Power Down and Active Power Down
– Write Data Mask
– Write Latency = 1
– 15.6μS Refresh interval (4K/64 mS Refresh), @ 0°C ≤ TA ≤ 85°C
– 3.9μS Refresh interval (4K/16 mS Refresh), @ 85°C < TA ≤ 105°C
– Maximum burst refresh cycle: 8